Verilog Code for a 4:1 MUX using a case statement

module mux (a,b,c,d,sel,out1);

        input a,b,c,d;
        input [1:0] sel;
        output reg out1;

        always @(*)
          case (sel)
            2’b00   : out1 = a;
            2’b01   : out1 = b;
            2’b10   : out1 = c;
            default : out1 = d;
          endcase
        endmodule