8-bit latch with gate and an asynchronous set

module latch (gate,d,set,q);

        input  gate,set;
        input  [7:0] d;
        output [7:0] q;
        reg    [7:0] q;

        always @(*)
          if (set)
             q <= 8’b00001111;
          else if (gate)
             q <= d;

       endmodule