D flip-flop with a positive edge clock and asynchronous clear

      module dff(clk, d, clr, q);
        input  clk, d, clr;
        output reg q;

        always @(posedge clk or posedge clr)
                if (clr)
                        q <= 1’b0;
                else
                        q <= d;

        endmodule

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