Verilog code for 4-bit unsigned up counter with a synchronous load with a constant

module counter (clk,sload,qout);

        input clk,sload;
        output [3:0] qout;
        reg [3:0] temp;

        always @(posedge clk)
          if (sload)
             temp <= 4’b1010;
          else
             temp <= temp + 1’b1;

        assign qout = temp;

        endmodule