Verilog code for 4-bit unsigned up counter with an asynchronous clear and a clock enable

module counter (clk,clr,ce,qout);

        input clk,clr,ce;
        output [3:0] qout;
        reg [3:0] temp;

        always @(posedge clk,posedge clr)
          if (clr)
             temp <= 4’b0000;
          else if (ce)
              temp <= temp + 1’b1;

        assign qout = temp;

        endmodule