Verilog code for 4-bit unsigned up counter with an asynchronous load

module counter_with_load(clk,load,d,q);

        input clk,load;
        input  [3:0] d;
        output [3:0] q;
        reg    [3:0] temp;

        always @(posedge clk or posedge load)
            if (load)
                 temp <= d;
            else
                 temp <= temp + 1’b1;

        assign q = temp;

        endmodule