Verilog code for 4-bit unsigned down counter with synchronous set

module down_counter (clk,set,q);

        input clk;
        input set;
        output [3:0] q;
        reg    [3:0] tmp;

        always @(posedge clk)
           if (set)
                tmp <= 4’b1111;
           else
                tmp <= tmp - 1’b1;

        assign q = tmp;

        endmodule