Verilog code for a 8-bit signed up counter with an asynchronous reset

module counter (clk, clr, qout);

        input clk,clr;
        output signed [7:0] qout;
        reg signed [7:0] temp;

        always @ (posedge clk,posedge clr)
           if (clr)
              temp <= 8’b00000000;
           else
              temp <= temp+1’b1;

        assign qout = temp;

        endmodule