Verilog code for a N-bit signed up counter with an asynchronous reset and a modulo maximum

module counter (clk,clr,qout);

       parameter N=4,MAX=(N*N);

       input clk,clr;
       output signed [N-1:0] qout;
       reg signed [N-1:0] count;

        always @ (posedge clk,posedge clr)
           if (clr)
                count <= 0;
           else
                count <= (count+1)%MAX;

        assign qout = count;

        endmodule