Verilog code for N-bit shift-left/shift-right register with a positive-edge clock, a serial in and parallel out

module shift (clk,si,left_right,pout);

        parameter N=8;

        input clk,si,left_right;
        output [N-1:0] pout;
        reg [N-1:0] tmp;

        always @(posedge clk)
           if (left_right == 1’b0)
               tmp <= {tmp[N-2:0],si};
           else
               tmp <= {si,tmp[N-1:1]};

        assign pout = tmp;

        endmodule