Verilog code for N-bit shift-left register with a positive-edge clock, a synchronous parallel load, a serial in and a serial out

module shift (clk,sload,si,d,so);

        parameter N=8;

        input clk, si, sload;
        input [N-1:0] d;
        output so;
        reg [N-1:0] tmp;

        always @(posedge clk)
           if (sload)
              tmp <= d;
           else
              tmp <= {tmp[N-2:0], si};

        assign so = tmp[N-1];

        endmodule