Verilog code for parity checker (even parity/odd parity)

         module parity_check (in1,even_out1,odd_out1);

        input in1;
        output even_out1,odd_out1;
        reg temp;

        always@(in1)
        begin
            temp <= ^in1;

            if(temp)
            begin
                even_out1 <= 1'b1;
                odd_out1  <= 1'b0;
            end
            else
            begin
                even_out1 <= 1'b0;
                odd_out1   <= 1'b1;
            end
        end

        endmodule