Verilog code for universal(dynamic) shift register

module sh_reg_dyn (si,load,dir,clk,pi,po);

parameter size = 4;

input si,clk,dir,load;
input [size-1:0] pi;
output [size-1:0] po;

reg [size-1:0] temp;

always @ (posedge clk)
//If load signal is high, parallel input is loaded in temp register     
  if(load)
        temp <= pi;
//If dir == 1 , makes left shift else right shift
  if(dir)
        temp <= {temp[size-2:0],si};
  else
        temp <= {si,temp[size-1:1]};

assign po = temp;

endmodule