VLSI Domain
Verilog code for tristate element using a combinational process and always block
~\Desktop\pracctice.v.html
module
three_state
(
sel
,
i
,
o
);
input
sel
,
i
;
output
o
;
reg
o
;
always
@(
sel
,
i
)
if
(
sel
)
o
=
i
;
else
o
=
1
’bZ
;
endmodule
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