Verilog code for 4-bit unsigned up counter with asynchronous clear

module up_counter (clk, clr, q);

        input clk;
        input clr;
        output [3:0] q;
        reg    [3:0] tmp;

        always @(posedge clk or posedge clr)
            if (clr)
                 tmp <= 4’b0000;
            else
                 tmp <= tmp + 1’b1;

        assign q = tmp;

        endmodule