Verilog code for unsigned 8-bit adder and subtractor

module add_sub(a,b,oper,res);

        input oper;
        input [7:0] a;
        input [7:0] b;
        output reg [7:0] res;

        always @*
           if (oper == 1’b0)
                res = a + b;
           else
                res = a - b;

        endmodule