Verilog code that infers 3:8 decoder

module decoder (sel, out1);

        input [2:0] sel;
        output reg [7:0] out1;

        always @(sel,out1)
           case (sel)
              3’b000  : out1 = 8’b00000001;
              3’b001  : out1 = 8’b00000010;
              3’b010  : out1 = 8’b00000100;
              3’b011  : out1 = 8’b00001000;
              3’b100  : out1 = 8’b00010000;
              //101,110 and 111 selector values are unused
              default : out1 = 8’bxxxxxxxx;
           endcase

        endmodule