parameter N=8;
//By varying the parameter value you can change the width of shift register
input [N-1:0] si;
input [1:0] sel;
output reg [N-1:0] so;
always @(si or sel)
case (sel)
2’b00 : so = si;
2’b01 : so = si << 1; //shifts by 1-bit
2’b10 : so = si << 2; //shifts by 2-bit
default : so = si << 3; //shifts by 3-bit
endcase
endmodule