Verilog code example using task

module task_calling (temp_a, temp_b, temp_c, temp_d);

input [7:0] temp_a, temp_c;
output [7:0] temp_b, temp_d;
reg [7:0] temp_b, temp_d;
//Uncomment the below line only when task is written in some other file
//`include "task.v"  

always @ (temp_a)
  convert (temp_a, temp_b);

always @ (temp_c)
  convert (temp_c, temp_d);

endmodule

task convert;
input [7:0] temp_in;
output [7:0] temp_out;
temp_out = (9/5) * ( temp_in + 32);
endtask