Verilog code for sequence detector (101101)

//sequence detector 101101

module fsm (rst,in1,clk,out1);

parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101;

input rst,in1,clk;
output reg out1;

reg [2:0] state;

always @(posedge clk)
  if (rst)
    begin
      state <= s0;
      out1  <= 0 ;
    end
  else
      case(state)
              s0 : if (in1) begin state <= s1; out1 <= 0 ; end
                    else     begin state <= s0; out1 <= 0 ; end
              s1 : if (in1) begin state <= s0; out1 <= 0 ; end
                    else     begin state <= s2; out1 <= 0 ; end
              s2 : if (in1) begin state <= s3; out1 <= 0 ; end
                    else     begin state <= s0; out1 <= 0 ; end
              s3 : if (in1) begin state <= s4; out1 <= 0 ; end
                    else     begin state <= s2; out1 <= 0 ; end
              s4 : if (in1) begin state <= s1; out1 <= 0 ; end
                    else     begin state <= s5; out1 <= 0 ; end
              s5 : if (in1) begin state <= s1; out1 <= 1 ; end
                    else     begin state <= s0; out1 <= 0 ; end
        default: if (in1) begin state <= s0; out1 <= 0 ; end
                    else     begin state <= s0; out1 <= 0 ; end
      endcase

endmodule