Verilog code for 4-bit latch with an inverted gate and an asynchronous preset

module latch (sel,d,pre,q);

        input  sel,pre;
        input  [3:0] d;
        output [3:0] q;
        reg    [3:0] q;

        always @*
           if (pre)
              q <= 4’b1111;
           else if (~sel)
              q <= d;

        endmodule