Verilog code for a 4-bit register with a positive edge clock, asynchronous set and clock enable

module 4bitreg (clk, d, ce, preset, q);

        input clk, ce, pre;
        input  [3:0] d;
        output [3:0] q;
        reg [3:0] q;

        always @(posedge clk or posedge preset)
            if (pre)
                 q <= 4’b1111;
            else if (ce)
                 q <= d;

        endmodule

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