Verilog code for 4-bit shift-left register with a positive-edge clock, asynchronous clear, serial in and serial out

module shift (clk,clr,si,so);

        input clk,si,clr;
        output so;
        reg [3:0] tmp;

        always @(posedge clk or posedge clr)
          if (clr)
             tmp <= 4’b0000;
          else
             tmp <= {tmp[2:0], si};

        assign so = tmp[3];

        endmodule