Verilog code for N-bit shift-left register with a negative-edge clock, clock enable, serial in and serial out

module shift (si,so,clk,ce);

        parameter N=8;

        input si,clk,ce;
        output so;
        reg [N-1:0] temp;

        always @(negedge clk)
           if (ce)
             begin
                temp <= temp << 1;
                temp[0] <= si;
             end

        assign so = temp[N-1];

        endmodule