Verilog code for 8-bit shift-left register with a positive-edge clock, a synchronous set, serial in and serial out

module shift (clk,sel,si,so);

        input clk,si,sel;
        output so;
        reg [7:0] tmp;

        always @(posedge clk)
          if (sel)
             tmp <= 8’b01010101;
          else
             tmp <= {tmp[6:0], si};

        assign so = tmp[7];

        endmodule