Verilog code for a 4-bit unsigned up accumulator with an asynchronous clear

module accumulator(clk,clr,din,qout);

        input clk, clr;
        input [3:0] din;
        output [3:0] qout;
        reg [3:0] temp;

        always @(posedge clk or posedge clr)
          if (clr)
              temp <= 4’b0000;
          else
              temp <= temp + din;

        assign qout = temp;

        endmodule