Verilog code for N-bit shift-left register with a positive-edge clock, serial in and serial out

module shift (clk,si,so);

        parameter N=8;

        input si,clk;
        output so;

        reg [N-1:0] temp;

        always @(posedge clk)
        begin
           temp <= temp << 1;
           temp[0] <= si;
        end

        assign so = temp[N-1];

        endmodule