Verilog code for a 4-bit unsigned up/down counter with an asynchronous clear

module counter (clk,clr,up_down,qout);

        input clk,clr,up_down;
        output [3:0] qout;
        reg    [3:0] temp;

        always @(posedge clk, posedge clr)
          if (clr)
             temp <= 4’b0000;
          else if (up_down)
             temp <= temp + 1’b1;
          else
             temp <= temp - 1’b1;

        assign qout = temp;

        endmodule