Verilog code for true dual port ram

module ram_tdp (clk, we1, we2, addr1, addr2, din1, din2, dout1, dout2);

parameter address_width = 5;
parameter data_width = 4;
parameter ram_depth = 1 << address_width;

input we1, we2, clk;
input [data_width-1:0] din1, din2;
input [address_width-1:0] addr1, addr2;

output reg [data_width-1:0] dout1, dout2;

reg [data_width-1:0] ram [ram_depth-1:0];

always @(posedge clk)
   if(we1)
        ram[addr1] <= din1;
    else
        dout1 <= ram[addr1];

always @(posedge clk)
    if(we2)
        ram[addr2] <= din2;
    else
        dout2 <= ram[addr2];

endmodule