Verilog code for serial-in parallel-out 8-bit shift-left register with a positive-edge clock

module shift (clk, si, po);

        input clk,si;
        output [7:0] po;
        reg    [7:0] temp;

        always @(posedge clk)
          temp <= {temp[6:0],si};

        assign po = temp;

        endmodule