Verilog code for N-bit shift-left register with a positive-edge clock, an asynchronous parallel load, serial in and serial out

module shift (clk,load,si,din,so);

        parameter N=8;

        input clk,si,load;
        input [N-1:0] din;
        output so;
        reg [N-1:0] tmp;

        always @(posedge clk or posedge load)
          if (load)
             tmp <= din;
          else
             tmp <= {tmp[N-2:0], si};

        assign so = tmp[N];

        endmodule