Verilog code using blocking and nonblocking assignments

module nonblocking(in1,clk,out1);

input in1,clk;
output reg out1;
reg w1,w2;

//This code refers to a shift register
always @(posedge clk)
begin
            w1    <= in1 ;
            w2    <= w1  ;
            out1  <= w2  ;
end

endmodule

//------------------------------------------------------------------------

module blocking(in1,clk,out1);

input in1,clk;
output reg out1;
reg w1,w2;

//This code refers to a D-ff with in1 as input & out1 as output
always @(posedge clk)
begin
            w1     =  in1;
            w2     =  w1 ;
            out1   =  w2 ;
end

endmodule