VLSI Domain
Verilog code for unsigned 8-bit adder with carry out
~\Desktop\pracctice.v.html
module
unsigned_adder
(
a
,
b
,
sum
,
co
);
input
[
7
:
0
]
a
;
input
[
7
:
0
]
b
;
output
[
7
:
0
]
sum
;
output
co
;
assign
{
co
,
sum
}
=
a
+
b
;
endmodule
Newer Post
Older Post
Home